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CMOSスタティックメモリ回路の電流テスト手法
http://hdl.handle.net/10295/1297
http://hdl.handle.net/10295/1297d83ccdc4-11c0-4fb5-ae52-925ce1d76154
名前 / ファイル | ライセンス | アクション |
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sozai11b1.pdf (594.6 kB)
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Item type | 学術雑誌論文 / Journal Article(1) | |||||
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公開日 | 2008-10-30 | |||||
タイトル | ||||||
タイトル | CMOSスタティックメモリ回路の電流テスト手法 | |||||
言語 | ||||||
言語 | jpn | |||||
キーワード | ||||||
主題Scheme | Other | |||||
主題 | Current Testing | |||||
キーワード | ||||||
主題Scheme | Other | |||||
主題 | CMOS Static RAM | |||||
キーワード | ||||||
主題Scheme | Other | |||||
主題 | I DDQ Testing | |||||
キーワード | ||||||
主題Scheme | Other | |||||
主題 | Design for Testability | |||||
資源タイプ | ||||||
資源タイプ識別子 | http://purl.org/coar/resource_type/c_6501 | |||||
資源タイプ | journal article | |||||
別タイトル | ||||||
その他のタイトル | Current Testing for CMOS Static RAMs to Reduce Testing Costs | |||||
著者 |
横山, 洋之
× 横山, 洋之× 玉本, 英夫× YOKOYAMA, Hiroshi× TAMAMOTO, Hideo |
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内容記述(抄録) | ||||||
内容記述タイプ | Other | |||||
内容記述 | In this paper, we discuss a current testing method, which aims to reduce testing costs on CMOS Static RAMs (SRAMs). As the fault models on a memory cell, we assume a hard short between two signal lines, a hard open on signal line, a transistor stuck-on fault, and a transistor stuck-open fault. Proposed test method is based on the simulation results of electrical behavior on the faulty memory cell. In this test method, decoder circuits and bit lines are modified to drive all the memory cells of SRAMs simultaneously. Since the faults are detected by only observing the power supply current, the test sequence becomes simple, and it does not dependent on the size of the memory cell array. |
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著者版フラグ | ||||||
出版タイプ | VoR | |||||
出版タイプResource | http://purl.org/coar/version/c_970fb48d4fbd8a85 | |||||
書誌情報 |
素材物性学雑誌 巻 11, 号 2, p. 5-11, 発行日 1998-12-01 |
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ISSN | ||||||
収録物識別子タイプ | ISSN | |||||
収録物識別子 | 09199853 | |||||
NCID | ||||||
収録物識別子タイプ | NCID | |||||
収録物識別子 | AN10140273 | |||||
出版者 | ||||||
出版者 | 日本素材物性学会 |