{"created":"2023-07-25T10:22:05.412477+00:00","id":1340,"links":{},"metadata":{"_buckets":{"deposit":"6cc4aeee-fcbc-42bc-8d7c-6bae397aea5b"},"_deposit":{"created_by":3,"id":"1340","owners":[3],"pid":{"revision_id":0,"type":"depid","value":"1340"},"status":"published"},"_oai":{"id":"oai:air.repo.nii.ac.jp:00001340","sets":["590:664:665:827"]},"author_link":["4687","4686","4684","4685"],"item_10001_alternative_title_1":{"attribute_name":"別タイトル","attribute_value_mlt":[{"subitem_alternative_title":"Current Testing for CMOS Static RAMs to Reduce Testing Costs"}]},"item_10001_biblio_info_7":{"attribute_name":"書誌情報","attribute_value_mlt":[{"bibliographicIssueDates":{"bibliographicIssueDate":"1998-12-01","bibliographicIssueDateType":"Issued"},"bibliographicIssueNumber":"2","bibliographicPageEnd":"11","bibliographicPageStart":"5","bibliographicVolumeNumber":"11","bibliographic_titles":[{"bibliographic_title":"素材物性学雑誌"}]}]},"item_10001_description_5":{"attribute_name":"内容記述（抄録）","attribute_value_mlt":[{"subitem_description":"In this paper, we discuss a current testing method, which aims to reduce\ntesting costs on CMOS Static RAMs (SRAMs). As the fault models on a memory\ncell, we assume a hard short between two signal lines, a hard open on signal\nline, a transistor stuck-on fault, and a transistor stuck-open fault. Proposed\ntest method is based on the simulation results of electrical behavior on the faulty\nmemory cell. In this test method, decoder circuits and bit lines are modified\nto drive all the memory cells of SRAMs simultaneously. Since the faults are\ndetected by only observing the power supply current, the test sequence becomes\nsimple, and it does not dependent on the size of the memory cell array.","subitem_description_type":"Other"}]},"item_10001_publisher_8":{"attribute_name":"出版者","attribute_value_mlt":[{"subitem_publisher":"日本素材物性学会"}]},"item_10001_source_id_11":{"attribute_name":"NCID","attribute_value_mlt":[{"subitem_source_identifier":"AN10140273","subitem_source_identifier_type":"NCID"}]},"item_10001_source_id_9":{"attribute_name":"ISSN","attribute_value_mlt":[{"subitem_source_identifier":"09199853","subitem_source_identifier_type":"ISSN"}]},"item_10001_version_type_20":{"attribute_name":"著者版フラグ","attribute_value_mlt":[{"subitem_version_resource":"http://purl.org/coar/version/c_970fb48d4fbd8a85","subitem_version_type":"VoR"}]},"item_creator":{"attribute_name":"著者","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"横山, 洋之"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"玉本, 英夫"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"YOKOYAMA, Hiroshi","creatorNameLang":"en"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"TAMAMOTO, Hideo","creatorNameLang":"en"}],"nameIdentifiers":[{}]}]},"item_files":{"attribute_name":"ファイル情報","attribute_type":"file","attribute_value_mlt":[{"accessrole":"open_date","date":[{"dateType":"Available","dateValue":"2017-02-16"}],"displaytype":"detail","filename":"sozai11b1.pdf","filesize":[{"value":"594.6 kB"}],"format":"application/pdf","licensetype":"license_note","mimetype":"application/pdf","url":{"label":"sozai11b1.pdf","url":"https://air.repo.nii.ac.jp/record/1340/files/sozai11b1.pdf"},"version_id":"7253e081-5d04-4110-bb61-6fd8b936eec1"}]},"item_keyword":{"attribute_name":"キーワード","attribute_value_mlt":[{"subitem_subject":"Current Testing","subitem_subject_scheme":"Other"},{"subitem_subject":"CMOS Static RAM","subitem_subject_scheme":"Other"},{"subitem_subject":"I DDQ Testing","subitem_subject_scheme":"Other"},{"subitem_subject":"Design for Testability","subitem_subject_scheme":"Other"}]},"item_language":{"attribute_name":"言語","attribute_value_mlt":[{"subitem_language":"jpn"}]},"item_resource_type":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"resourcetype":"journal article","resourceuri":"http://purl.org/coar/resource_type/c_6501"}]},"item_title":"CMOSスタティックメモリ回路の電流テスト手法","item_titles":{"attribute_name":"タイトル","attribute_value_mlt":[{"subitem_title":"CMOSスタティックメモリ回路の電流テスト手法"}]},"item_type_id":"10001","owner":"3","path":["827"],"pubdate":{"attribute_name":"公開日","attribute_value":"2008-10-30"},"publish_date":"2008-10-30","publish_status":"0","recid":"1340","relation_version_is_last":true,"title":["CMOSスタティックメモリ回路の電流テスト手法"],"weko_creator_id":"3","weko_shared_id":-1},"updated":"2023-07-25T11:54:05.308705+00:00"}