@article{oai:air.repo.nii.ac.jp:00001340,
 author = {横山, 洋之 and 玉本, 英夫 and YOKOYAMA, Hiroshi and TAMAMOTO, Hideo},
 issue = {2},
 journal = {素材物性学雑誌},
 month = {Dec},
 note = {In this paper, we discuss a current testing method, which aims to reduce
testing costs on CMOS Static RAMs (SRAMs). As the fault models on a memory
cell, we assume a hard short between two signal lines, a hard open on signal
line, a transistor stuck-on fault, and a transistor stuck-open fault. Proposed
test method is based on the simulation results of electrical behavior on the faulty
memory cell. In this test method, decoder circuits and bit lines are modified
to drive all the memory cells of SRAMs simultaneously. Since the faults are
detected by only observing the power supply current, the test sequence becomes
simple, and it does not dependent on the size of the memory cell array.},
 pages = {5--11},
 title = {CMOSスタティックメモリ回路の電流テスト手法},
 volume = {11},
 year = {1998}
}