{"created":"2023-07-25T10:21:43.957969+00:00","id":848,"links":{},"metadata":{"_buckets":{"deposit":"b63fdf20-6119-4050-8857-da147c6cffe9"},"_deposit":{"created_by":15,"id":"848","owners":[15],"pid":{"revision_id":0,"type":"depid","value":"848"},"status":"published"},"_oai":{"id":"oai:air.repo.nii.ac.jp:00000848","sets":["590:664:671:673"]},"author_link":[],"item_10001_biblio_info_7":{"attribute_name":"書誌情報","attribute_value_mlt":[{"bibliographicIssueDates":{"bibliographicIssueDate":"2006-11-01","bibliographicIssueDateType":"Issued"},"bibliographicIssueNumber":"1/2","bibliographicPageEnd":"6","bibliographicPageStart":"1","bibliographicVolumeNumber":"14","bibliographic_titles":[{"bibliographic_title":"International Journal of the Society of Materials Engineering for Resources","bibliographic_titleLang":"en"}]}]},"item_10001_description_5":{"attribute_name":"内容記述","attribute_value_mlt":[{"subitem_description":"The evolution of the integrated circuit technology during the last 3 decades has been based on an increasing accuracy of the manufacturing process. With thisprinciple and by using a quality control at the end of the production line (Test Technology) the semiconductor industry has reached very high productivity levels. However, with technology reaching criticalsizes ( < 65 nm) the manufacturing controlis startingto failand new design principles have to be introduced to be able to produce functional chips from low quality components. In this article two scenarios partially addressing the problem with gradual introduction of redundancy are considered: the scenario of the era at the end of the CMOS Moore's Law and the expected next scenario of nanoelectronic technology using new emergent devices. In the paper techniques for the design of robust electronic systems in spite of the low quality of components are presented for the two scenarios.","subitem_description_language":"en","subitem_description_type":"Abstract"}]},"item_10001_publisher_8":{"attribute_name":"出版者","attribute_value_mlt":[{"subitem_publisher":"The Society of Materials Engineering for Resources of Japan","subitem_publisher_language":"en"}]},"item_10001_relation_25":{"attribute_name":"関連情報","attribute_value_mlt":[{"subitem_relation_type":"isIdenticalTo","subitem_relation_type_id":{"subitem_relation_type_id_text":"http://doi.org/10.5188/ijsmer.14.1","subitem_relation_type_select":"DOI"}}]},"item_10001_version_type_20":{"attribute_name":"出版タイプ","attribute_value_mlt":[{"subitem_version_resource":"http://purl.org/coar/version/c_970fb48d4fbd8a85","subitem_version_type":"VoR"}]},"item_1724099666130":{"attribute_name":"収録物識別子","attribute_value_mlt":[{"subitem_source_identifier":"1347-9725","subitem_source_identifier_type":"PISSN"},{"subitem_source_identifier":"AA1095475X","subitem_source_identifier_type":"NCID"}]},"item_access_right":{"attribute_name":"アクセス権","attribute_value_mlt":[{"subitem_access_right":"open access","subitem_access_right_uri":"http://purl.org/coar/access_right/c_abf2"}]},"item_creator":{"attribute_name":"作成者","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"RuBio, Antonio","creatorNameLang":"en"}]},{"creatorNames":[{"creatorName":"Martorell, Ferran","creatorNameLang":"en"}]},{"creatorNames":[{"creatorName":"Moll, Francesc","creatorNameLang":"en"}]}]},"item_files":{"attribute_name":"ファイル情報","attribute_type":"file","attribute_value_mlt":[{"accessrole":"open_date","date":[{"dateType":"Available","dateValue":"2017-02-16"}],"displaytype":"detail","filename":"ijsmer14a.pdf","filesize":[{"value":"884.6 kB"}],"format":"application/pdf","licensetype":"license_note","mimetype":"application/pdf","url":{"label":"ijsmer14a.pdf","url":"https://air.repo.nii.ac.jp/record/848/files/ijsmer14a.pdf"},"version_id":"99a92941-1ecb-44f3-9910-e4df7f6631e6"}]},"item_keyword":{"attribute_name":"キーワード","attribute_value_mlt":[{"subitem_subject":"Integrated circuit technology","subitem_subject_language":"en","subitem_subject_scheme":"Other"},{"subitem_subject":"manufacturing yield","subitem_subject_language":"en","subitem_subject_scheme":"Other"},{"subitem_subject":"redundant design","subitem_subject_language":"en","subitem_subject_scheme":"Other"},{"subitem_subject":"quality of electronic components","subitem_subject_language":"en","subitem_subject_scheme":"Other"}]},"item_language":{"attribute_name":"言語","attribute_value_mlt":[{"subitem_language":"eng"}]},"item_resource_type":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"resourcetype":"journal article","resourceuri":"http://purl.org/coar/resource_type/c_6501"}]},"item_title":"Designing Circuits from Imperfect Components in VISI Giga-scale Technologies","item_titles":{"attribute_name":"タイトル","attribute_value_mlt":[{"subitem_title":"Designing Circuits from Imperfect Components in VISI Giga-scale Technologies","subitem_title_language":"en"}]},"item_type_id":"10001","owner":"15","path":["673"],"pubdate":{"attribute_name":"PubDate","attribute_value":"2008-03-07"},"publish_date":"2008-03-07","publish_status":"0","recid":"848","relation_version_is_last":true,"title":["Designing Circuits from Imperfect Components in VISI Giga-scale Technologies"],"weko_creator_id":"15","weko_shared_id":-1},"updated":"2024-08-25T18:13:08.378143+00:00"}