@article{oai:air.repo.nii.ac.jp:00003326,
 author = {小原, 仁 and Koloko, Labson and Obara, Hitoshi},
 journal = {秋田大学大学院理工学研究科研究報告, SCIENTIFIC AND TECHNICAL REPORTS OF GRADUATE SCHOOL OF ENGINEERING SCIENCE, AKITA UNIVERSITY},
 month = {Nov},
 note = {Since C. Clos published his seminal work on three-stage switching networks in 1953, the Clos architecture has offered a most practical and efficient design solution for implementing large-scale switching networks to date.There are a great number of published articles applying the Clos architecture to space switches, time-division multiplexed switches, packet/ATM switches, optical switches, among others. However, to our knowledge, there are very few researches aiming to improve performances of the Clos architecture itself. In this paper we give out some redundancy in the Clos architecture for the first time, e.g. idle ports left unused, and examine some techniques to enhance its performances by using the redundancy. Although this paper focuses on the back ground and scope of the study, we fix our research goals and briefly discuss possible techniques in this paper. Our new design principles of the Clos networks will appear elsewhere in the near future.},
 pages = {9--14},
 title = {3 段Clos スイッチ網の性能改善に関する研究（その1）− 研究の背景とスコープ−},
 volume = {39},
 year = {2018}
}